1. Field of the Invention
The present invention relates to a bridge fault removal apparatus, a bridge fault removal method, and a computer readable medium comprising computer program code for removing bridge fault. Particularly the invention relates to the bridge fault removal apparatus, the bridge fault removal method, and the computer readable medium comprising computer program code for removing a bridge failure in a semiconductor integrated circuit such as LSI (Large Scale Integration) manufactured by a microfabrication process.
2. Related Art
In the recent semiconductor integrated circuit such as LSI, dust tends to adhere between interconnections to establish conduction with the finer microfabrication process and the multi-layered interconnection (including resistivity). When the interconnections become different potentials, a bridge failure incidence ratio in which a faulty signal propagates to the outside of LSI to cause a malfunction is rapidly increased. For example, the microfabrication process reaches 32 nm, and lengths of proximity interconnection wires exceed 100 m even in LSI having an average size. Therefore, the bridge failure incidence ratio is extremely enhanced.
Conventionally, in a test (hereinafter referred to as “bridge fault test”) for such bridge failure in LSI, a pair of proximity interconnection wires is extracted from layout information on an object LSI as a bridge fault having a high possibility of causing the bridge failure. Then, a test pattern is generated so as to detect the bridge fault, and is applied to LSI so as to effectively detect the bridge failure. Particularly, practical use of a bridge fault IDDQ test that can be comparatively easily realized has been mainly developed. In the bridge fault IDDQ test, a static source current (IDDQ (IDD Quiescent)) is measured in each bridge fault test pattern, and an abnormal IDDQ that is passed when the bridge fault in which the pair of interconnections becomes (1,0) or (0,1) includes the bridge failure is measured to detect the bridge failure.
However, in LSI used in a high-speed product manufactured through the microfabrication process, because ordinary IDDQ value is largely increased, the IDDQ test is hard.
Bridge fault test using a logical level detection is also well known in addition to the IDDQ test. Examples of the bridge fault test using the logical level detection include a test in which a bridge fault type such as “Wired-AND” and “Wired-OR” is dealt with in order to simply test LSI and a test in which an object bridge fault is the bridge failure correctly modeled by a complicated combination of the layout information and circuit information.
Four kinds of bridge faults, that is, “Wired-AND”, “Wired-OR”, “A-Dominate”, and “B-Dominate”, are detected in the ordinal bridge fault test using the logical level detection. The kind of the bridge fault is determined by elements that drive the two signal lines constituting the bridge, inputs to the elements, a resistance value between short-circuited signals, a cell that receives each signal, and a logical threshold of a corresponding input terminal. Therefore, in the bridge fault test, it is necessary to properly extract these pieces of information. In the bridge fault test, when accuracy of the test result exceeds a predetermined level, an effect that is obtained by improving the accuracy of the test result tends to be weakened. Therefore, it is necessary to realize the bridge fault test in which the practical accuracy is easy to achieve.
However, it is extremely difficult to completely extract the pieces of information. Particularly, in the bridge fault test for LSI, a large amount of CPU (Central Processing Unit) resource is necessary. Therefore, the bridge fault test achieving the practical accuracy is hardly realized.
On the other hand, an ATPG (Automatic Test Pattern Generation) tool is well known as a tool that easily realizes the IDDQ test and the bridge fault test (for example, see JP-A No. 2007-147503 (Kokai)).
However, in the ATPG tool, because the test pattern is generated according to a generation algorithm based on a scan test technique that is basic and is designed to make a test easy, the number of finally-detectable bridge faults is determined by the number of test patterns for an LSI logical net including an easily-testable design circuit such as a scan. As a result, an undetected bridge fault always remains, and the bridge failure cannot be detected even if the bridge failure occurs in the pair of interconnections corresponding to the bridge fault. Therefore, the bridge failure incidence ratio cannot sufficiently be reduced. Additionally, in the ATPG tool, because some of the bridge faults remain undetected when only a few test patterns are used, a test quality is hardly improved. As a result, since it is difficult to shorten an IDDQ measuring time compared with other test techniques (currently, at least one millisecond to several milliseconds are necessary for one pattern), a large effect cannot be obtained even if the ATPG tool is used in the IDDQ test in which the improvement of test quality is obtained by few test patterns.
Particularly, the undetected bridge fault that is not determined by the ATPG tool as untestable can be logically activated. As a result, in the case where the bridge failure corresponding to the bridge fault occurs in a product LSI, the product LSI that is shipped as non-defective can be activated to become a defective product when the product LSI operated on a user's system. Additionally, even if the product LSI is returned and is tested again, the returned product LSI passes the test. Therefore, the cause of the bridge failure can be left unclear.
On the other hand, in order to reduce the crosstalk failure, a technique of widening a distance between proximity interconnections to locally lower the bridge failure incidence ratio is well known (for example, see JP-A No. 2008-21001 (Kokai) and JP-A No. 2007-179416 (Kokai)).
Although the conventional technique widens the distance between the proximity interconnection wires that are disposed in parallel at a large length with respect to given LSI layout information, resulting in increase of an area of LSI. Therefore, it is difficult to lower the bridge failure incidence effectively by widen the distance between the proximity interconnection wires. Therefore, the bridge failure incidence ratio in LSI cannot sufficiently be reduced by the conventional technique.